1. Field of the Invention
The invention relates to a photomask for exposing a chip pattern onto a wafer and a method for exposing a chip pattern.
This application is a counterpart of Japanese patent application, Serial Number 304002/2002, filed Oct. 18, 2002, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
Before mass-producing chips, a prototype of a chip is always fabricated and the prototype of the chip has to be evaluated. In order to manufacture the prototype of the chip, a reticle mask (one type of a photomask) on which a chip pattern, corresponding to a prototype of the chip, is formed and fabricated.
For a reticle mask for prototype use, a reticle mask 100 on which only the same types of chip patterns A are formed, as shown in FIG. 15(A), and a reticle mask (multichip mask) 102 on which multiple types of chip patterns A, B, C are formed at the same ratio, and the like, as shown in FIG. 15(B), have been conventionally used.
There is an advantage that the reticle mask 100 for prototype use can be used for mass production, as if there is no problem. However, if any problem arises in the chip patterns A, it is necessary to design and fabricate again a reticle mask for forming a chip pattern for prototype use in place of the chip patterns A, and hence it takes time to make the transition to the mass-production. Further, for the multichip mask 102, it is necessary to design and fabricate again a mask for mass-production so as to utilize the exposure area of the projection exposure apparatus (the apparatus is called as an aligner or a stepper) for mass-production to the greatest extent, and hence there arises a problem of increase of cost.
Further, as shown in FIG. 16, there is proposed a method of exposing only an intended chip of a multichip mask 104 on which multiple (four types in FIG. 16) different patterns are formed onto a wafer 108 using a projection lens 106, for example, as disclosed in Japanese Laid-Open Patent No. 11-305418, and also there is proposed a method of exposing only an intended chip on a wafer while shielding an exposure area other than the intended chip, for example, as disclosed in Japanese Laid-Open Patent No. 06-020911.
However, these methods have a problem that it takes much time for processing chips because the exposure area is not utilized to the greatest extent.